ERCIM News No.37 - April 1999

Designing High-speed Communication Systems

by Dimitrios N. Serpanos

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High-speed transmission technology experiences significant progress for over a decade. The development and deployment of high-speed links in the business environment and to the home has triggered the development of a wide range of networks and services. As a result, the design of communication systems faces significant performance challenges, especially in light of the requirements for delivery of real-time traffic (multimedia).

The main problem in designing high-speed communication systems, ie adapters, bridges, routers, etc., is the throughput preservation problem: the problem to preserve the throughput of a high-speed link to applications through the protocol stack(s) implemented in a system. Solution to this problem requires the development of ‘intelligent’ communication system architectures, which implement high-speed data movement and protocol processing that meet the necessary performance requirements.

We are working on modular, scalable architectures for communication systems, because they are required to implement a wide range of functions and to meet the performance requirements of links as they scale to higher speeds. Considering the wide adoption and deployment of ATM technology, we focus on ATM systems, because they have demanding requirements, especially considering the scalability of the SDH/SONET physical layer. In our efforts, we evaluate and explore alternative technologies in order to obtain high performance systems at low cost.

An important module in high-speed communication systems is the memory manager, which manages logical data structures - typically queues - efficiently and enables high-speed data transfers between system memory and link interfaces. We have developed a high-speed, scalable and re-usable Queue Manager, suitable for a wide range of ATM systems, such as workstation adapters, switches, routers, etc. The Queue Manager is a special-purpose processor that executes memory management instructions. To achieve re-usability, we have analyzed the requirements of the most common ATM functions (flow control, segmentation-and-re-assembly, etc.) and identified an instruction set that is sufficient to implement these functions. To achieve scalability, we have identified a minimal set of instructions as well as a minimal set of data structures to support. We have developed an architecture and several hardware implementations, which provide increasing performance at the cost of more complex hardware. A typical low cosqueues of t implementation supports 1024 8192 ATM cells and performs an Enqueue and a Dequeue operation in 132ns and 198ns, respectively. Such an implementation supports ATM systems with aggregate throughput close to 1 Gbps.

Considering the processing power that exists in some systems in the form of embedded processors, we have developed a software implementation for embedded systems as well, using the CYCLONE evaluation board with the Intel i960 processor at 40 MHz. The average delays of the Enqueue and Dequeue operations in the software implementation are 0.75 and 0.95 microseconds, respectively. We have evaluated the performance, cost and scalability of all implementations, so that one can choose the solution with the desired characteristics.

The Queue Manager provides the support for efficient queue management and fast data movement in an ATM system, but it is necessary to provide additional support in order to implement Quality-of-Service (QoS) in data transmission; typically this is achieved with adoption of priorities. Scheduling of outgoing traffic constitutes an additional challenge. In this direction, we have designed in our lab an efficient scheduler that uses weighted round-robin for QoS. The scheduler operates in co-operation with the Queue Manager providing a complete solution in a prototype 4x1 ATM concentrator with 155 Mbps Sonet links.

As design methodologies and semiconductor technology progress, we can provide improved architectures and designs that exploit these advances. We are currently developing modules with more sophisticated and efficient architectures, targeting support of an increased number of functions and scalability to the higher speeds required by the emerging gigabit networks.

Please contact:

Dimitrios Serpanos - ICS-FORTH
Tel: +30 81 391663
E-mail: serpanos@ics.forth.gr