ERCIM News No.37 - April 1999

High-Performance ATM Switching: the ATLAS I Single Chip Switch

by Dionisios N. Pnevmatikatos

Asynchronous Transfer Mode (ATM) networks have become mainstream for wide area networks (WANs) and also in local area networks. They are based on packet switching, where 48 bytes of data together with a 5 header form the transfer unit called cell. This fixed packet size allows the parallel processing of cells inside the relay switches achieving high transmission throughput. ATM was originally designed to carry voice traffic, and as a consequence, ATM networks can efficiently handle voice, video and other types of traffic making them ideal for multimedia-type applications.

ATLAS I (ATm multi-LAne backpressure Switch One) is a high performance, single chip ATM switch designed in the Computer Architecture and VLSI Systems Division, of the Institute of Computer Science of FORTH. It is being developed within the ASICCOM Project, funded by the European Union ACTS Programme.

The ASICCOM Consortium includes two ERCIM members, FORTH and SINDEF. The other partners of ASICCOM are industrial partners (INTRACOM, Greece; ST Microelectronics, France and Italy; BULL, France), telecom operators (TELENOR, Norway; TELEFONICA, Spain), and research institutes (Poli. di Milano, Italy; Democritos, Greece). ATLAS I combines several desirable features such as a large number of links, high bandwidth links, advanced operating features, large buffer space and hooks for more efficient network management.

ATLAS I is a 6 million transistor chip designed in a 0.35 micron CMOS technology with five metal layers provided by ST Microelectronics. It features 16 input and 16 output ports (links) each operating at 622Mbits/s for an aggregate outgoing throughput of 10Gbits/s; the links use the IEEE 1355 ‘HIC/HS’ protocol. The switch operates at 50 MHz and achieves a sub-microsecond cell cut-through latency. Buffer space for the ATM cells is provided in the form of a 256-entry shared buffer, which is split into multiple logical output queues; ATLAS I also supports three levels of priorities, multicasting and header translation.

The most distinctive and innovative feature of ATLAS I is its (optional) credit-based flow control (backpressure). A cell in a backpressured service class (priority level) can only depart if it acquires both a buffer-pool credit for its outgoing link and a flow-group credit for its connection. A flow group is a set of connections that are flow-controlled together; ATLAS I supports up to 32 thousand flow groups. Credit-based flow control is useful in building switching fabrics with internal backpressure that provide the high performance of output queueing at the low cost of input buffering, and in making ATM sub-networks that never drop cells of data connections while fully and fairly utilizing all the available transmission capacity. An evaluation performed at FORTH shows that the credit protocol offers superior performance, especially in isolating well-behaved connections from bursty and hot-spot traffic.

ATLAS I also provides for efficient network load monitoring by means of accelerated Cell Loss Probability (CLP) measurement hardware. Very often in high-speed networks the probability of cell loss (for non-backpressured traffic) is very small, and measuring the CLP requires a very long observation period. The ATLAS I CLP hardware measures the cell loss rate of an emulated set of small buffers. Software can then use these measurements (over short periods of time) to extrapolate the CLP of the actual traffic. ATLAS I also provides hooks for switch management through the network. Special management cells are addressed to an internal management port, which can execute read and write commands to any of the internal structures of the switch. The results of the operations are packed in a reply cell and returned to the sender. Security is achieved by only accepting management cells from designated input links and connections.

ATLAS I is a powerful building block for the construction of ATM networks. The large number of links of the switch minimizes the number of switches needed for the construction of a network, as well as the delay (measured in hops) through the network itself. In addition the smaller number of chips reduces the physical dimensions of the network and increases its reliability. The advanced flow-control features of ATLAS I allow the fair and efficient use of the network bandwidth in a mixture of services ranging from real-time, guaranteed quality-of-service to best-effort, bursty and flooding traffic.

Furthermore, the versatility in the management of the individual switches allows for the creation of powerful network management software.

ATLAS I was fabricated by ST Microelectronics, Crolles, France, in December 1998-January 1999, and is currently being packaged; we will proceed to testing by placing the chips in a demonstration system that was built by Intracom, Sindef and Telenor. Future interest includes the commercial exploitation of the chip, and further development work in ATLAS-to-SONET interfacing, and in flow-control and weighted round-robin scheduling architectures.

For more information on the ATLAS I switch see:

Please contact:

Dionisios Pnevmatikatos - ICS-FORTH
Tel: +30 81 391657

return to the ERCIM News 37 contents page